A typical multi-layered substrate assembly, which is also referred to as a Pin Grid Array (PGA), has a multitude of individual circuits within it. In order to plate the exposed pins and solder pads by electrodeposition, it is necessary to electrically short each pin or circuit to the cathode. A number of techniques are currently used to accomplish this purpose.
In one method, known as tie-bar plating, a branch is designed into each circuit and leads to an edge of the substrate. A plating fixture can be constructed to short the circuits through a grounding contact with one or more edges of the substrate. This approach requires an array of parallel conductors leading to the edge of the substrate from each of the circuits in the assembly. For high speed integrated circuit devices, these parallel conductors form antennas that can cause noise within the substrate assembly during operation. This method is therefore not useful for high speed devices.
In certain PGA's, such as multiple chip modules, some circuits are connected to each other in a pad-to-pad connection and do not utilize a pin. Accordingly, some pins are not electrically connected to the substrate edges. These floating pins are not grounded and therefore do not get plated in a substrate-based tie-bar plating process.
In other methods, such as through-pin plating, a fixture makes contact with the ends of the pins. In PGA's in which every circuit terminates at at least one pin, every circuit element is thus shorted to a common point. The grounding element for contacting each of the pins, however, covers the pin side of the substrate assembly and restricts the flow of the plating bath. The result is that the plate thickness is typically thicker around the edges of the substrate than in the center. These contacting elements are also generally expensive and difficult to construct.
In interstitial pin arrays, each row of pins is staggered relative to each other so that each pin of a row is transversely aligned with a space in each of the adjacent rows of pins. Interstitial pin arrays generally provide more circuits, and the plating difficulties noted above are further extenuated.